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ZACH'S BLOG
Clock and Data Recovery PLL Design Considerations in 0.1 um CMOS
This post links to a paper that discusses clock and data recovery PLL design considerations in 0.1 um CMOS. Link:...
Implementing a 5-bit Folding and Interpolating Analog to Digital Converter
This post links to a paper presenting the physical design of a 5-bit folding and interpolating analog-to-digital converter. Link:...
A Machine to Support Autonomic Computing
This post links to a 2005 paper that delved into the world of autonomic computing from IBM's Autonomic Computing initiative. This paper...
AWS Free Tier At-A-Glance
This post is an AWS Free Tier At-A-Glance with links to instance names and terms. AWS Free Tier At-A-Glance COMPUTE Amazon EC2 / 12...
Unlocking FPGA Magic: From HDL to Hardware
Welcome to the world of FPGA design, where your ideas can come to life in silicon! This blog post discusses common processes and tools to...
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