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Xilinx's Zynq UltraScale+ MPSoC Diagrams are Wrong

April 6, 2018

 

This post presents a bug in the Zynq UltraScale+ MPSoC diagrams at xilinx.com.

 

All of the diagrams on the Zynq UltraScale+ MPSoC Product Landing Page share a common problem.

 

Here's the Application Processing Unit excerpt from a larger block diagram at link:

 

Look at where they put the ARM Cortex-A53 text:

 Are there 4 ARM Cortex-A53's? There are not. There is _one_ Cortex-A53 with four cores that contain one Armv8-A CPU each.

 

Arm documents the Cortex-A53 more accurately at the Cortex-A53 site:

 

So the diagram from Xilinx should look like:

 

Xilinx makes the same mistake with the R cores as well.

 

 

Reference

 

Find all the bugs image found at link.

 

 

 

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