Change the Boot Mode of the Xilinx Zynq UltraScale+ MPSoC from XSCT
This post show you how to change the boot mode of the Zynq UltraScale+ MPSoC from XSCT.
The following sequence changes to JTAG boot mode:
Big thanks to Krishna Chaitanya (LinkedIn) for sharing this awesome method!
Being able to change the boot mode remotely helps debug. Typically, the user will change boot from from whatever it is to JTAG Boot to load a custom build.
By writing the new boot mode to BOOT_MODE_USER (CRL_APB) Register @ 0xff5e0200 and triggering a software reset, the MPSoC will use the mode you wrote, not the mode of the strapping pins.
Here are sequences for each boot mode:
PJTAG (MIO #0)
PJTAG (MIO #1)
SD1 LS (3.0)
Table is available here as an Excel.
BOOT_MODE_USER (CRL_APB) Register
BOOT_MODE_USER (CRL_APB) Register Bit-Field Summary