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Change the Boot Mode of the Xilinx Zynq UltraScale+ MPSoC from XSCT

April 25, 2018

This post show you how to change the boot mode of the Zynq UltraScale+ MPSoC from XSCT. 

 

TL;DR 

 

The following sequence changes to JTAG boot mode: 

 

 

Thanks!

 

Big thanks to Krishna Chaitanya (LinkedIn) for sharing this awesome method!

 

 

Motivation

 

Being able to change the boot mode remotely helps debug. Typically, the user will change boot from from whatever it is to JTAG Boot to load a custom build. 

 

By writing the new boot mode to BOOT_MODE_USER (CRL_APB) Register @ 0xff5e0200 and triggering a software reset, the MPSoC will use the mode you wrote, not the mode of the strapping pins.

 

 

Sequences

 

Here are sequences for each boot mode:

 

JTAG

Quad-SPI (24b)

 

 

Quad-SPI (32b)

 

SD0 (2.0)

 

 

NAND

 

SD1 (2.0)

 

eMMC (1.8V)

 

USB (2.0)

 

PJTAG (MIO #0)

 

PJTAG (MIO #1)

 

SD1 LS (3.0)

 

 

 

 

References

  • Zynq UltraScale+ MPSoC Register Reference @ link

  • CSS Tables @ link 

 

Boot Modes

Table is available here as an Excel.

 

0xff5e0200 Documentation

 

BOOT_MODE_USER (CRL_APB) Register

 

 

Description

 

 

 

BOOT_MODE_USER (CRL_APB) Register Bit-Field Summary

 

 

 

 

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