• Zach Pfeffer

QSPI24, 24-bit addressing, 3-byte addressing QSPI32, 32-bit addressing, 4-byte addressing


This page discusses what the terms QSPI24 and QSPI32 probably mean, their likely origins and the terms relationship to the terms: 24-bit addressing, 32-bit addressing, 3-byte address mode and 4-byte address mode. I created it because I couldn't find this information from a few Google searches.

TL;DR

QSPI24 means 24-bit addressing which also means 3-byte address mode and that QSPI32 means 32-bit addressing which also means 4-byte address mode

QSPI24, 24-bit addressing, 3-byte addressing QSPI32, 32-bit addressing, 4-byte addressing

3-byte and 4-byte address modes

Micron lists "3-byte and 4-byte address modes" in at least their:

Micron Serial NOR Flash Memory 1.8V, Multiple I/O, 64KB Sector Erase MT25QU01GBBB datasheet @ link.

QSPI24 and QSPI32 / 24-bit and 32-bit addressing

A Google search for QSI24 and a Google search for QSI32 only return Xilinx originated content. For this reason, I am concluding that these terms came from Xilinx.

In the AR# 65463 Xilinx also lists:

  • QSPI24: 24-bit addressing

  • QSPI32: 32-bit addressing

Conclusion

Based on this evidence I'm concluding the QSPI24 and QSPI32 are terms Xilinx invented. At least Micron uses the terms "3-byte and 4-byte address modes." I'm also concluding that QSPI24 means 24-bit addressing which also means 3-byte address mode and that QSPI32 means 32-bit addressing which also means 4-byte address mode.

Table of Supported Devices

AR# 65463 - Zynq UltraScale+ MPSoC - What devices are supported for configuration? lists the following table. I've added links to the relevant parts:

References

1. Paste-in an Excel table and generate an HTML table with link.

2. Tip to reformat an HTML file in Vim found at link:

Set the following option:

:filetype indent on :set filetype=html # abbrev - :set ft=html :set smartindent # abbrev - :set si

Then move the cursor to the top of the file and indent to the end gg =G or select the desired text to indent and hit = to indent it.

3. AR# 65463 - Zynq UltraScale+ MPSoC - What devices are supported for configuration? contained the table data

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